Efficient Fine-Grain Synchronization on a Multi-Core Chip Architecture: A Fresh Look

Multi-core chip architectures are becoming mainstream, permitting increasing on-chip parallelism through hardware support for multithreading. Fine-grain synchronization is essential to the effective utilization of the capacity provided by future high-performance multi-core architectures. However, there are also new challenges realizing such fine-grain synchronization in large-scale multi-core chip architectures – such as the IBM Cyclops-64 chip that contains more than 100 processing cores and employs a memory organization with explicitly addressable memory segments instead of data cache. This paper presents a fresh look at the challenges and proposes a scalable solution for fine-grain synchronization that efficiently enforces mutual exclusion and read-after-write data-dependencies between concurrent threads. Using the Cyclops-64 chip architecture as a case study, we illustrate how to use a small Synchronization State Buffer (SSB) associated with each memory bank to accelerate the fine-grain synchronization by recording and managing the states of frequently synchronized data units with modest hardware extensions. We demonstrate the effectiveness and efficiency of the proposed solution. • For mutual exclusion: Using distributed fine-grain locking at each of the memory units, we avoid the unnecessary serialization of operations on different elements of the same concurrent data structure and achieve this goal efficiently. • For read-after-write data-dependencies synchronization: our method encourages the exploration of do-across style of loop-level parallelism where loop-carried data dependencies can often be directly implemented by the application of the fine-grain synchronization operations and the removal of useless barriers. The experimental results demonstrate significant performance gain due to the use of the above fine-grain synchronization solutions.